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integrated circuit systems, inc. general description features ics9148-12 block diagram pentium/pro tm system clock chip 9148-12 rev f 4/1/99 pentium is a trademark on intel corporation. ? cpu outputs are stronger drive for multiple loads per pin (ie cpu and nb on one pin) ? generates system clocks for cpu, ioapic, sdram, pci, plus 14.314 mhz ref(0:1), usb, plus super i/o ? supports single or dual processor systems ?i 2 c serial configuration interface provides output clock disabling and other functions ? mode input pin selects optional power management input control pins ? two fixed outputs separately selectable as 24 or 48mhz ? separate 2.5v and 3.3v supply pins ? 2.5v or 3.3v outputs: cpu, ioapic ? 3.3v outputs: sdram, pci, ref, 48/24 mhz ? cpu 3.3_2.5# logic pin to adjust output strength ? no power supply sequence requirements ? uses external 14.318mhz crystal ? 48 pin 300 mil ssop and 240 mil tssop ? output enable register for serial port control: 1 = enable 0 = disable the ics9148-12 is a clock synthesizer chip for pentium and pentiumpro cpu based desktop/notebook systems that will provide all necessary clock timing. features include four strong cpu, seven pci and eight sdram clocks. two reference outputs are available equal to the crystal frequency. stronger drive cpuclk outputs typically provide greater than 1 v/ns slew rate into 20pf loads. this device meets rise and fall requirements with 2 loads per cpu output (ie, one clock to cpu and nb chipset, one clock to two l2 cache inputs). pwr_dwn# pin allows low power mode by stopping crystal osc and pll stages. for optional power management, cpu_stop# can stop cpu (0:3) clocks and pci_stop# will stop pciclk (0:5) clocks. cpu and ioapic output buffer strength controlled by cpu 3.3_2.5# pin to match vddl voltage. pciclk outputs typically provide better than 1v/ns slew rate into 30pf loads while maintaining 505% duty cycle. the ref clock outputs typically provide better than 0.5v/ns slew rates. the ics9148-12 accepts a 14.318mhz reference crystal or clock as its input and runs on a 3.3v core supply. functionality vdd (1:4) 3.3v10%, vddl1, 2 2.55% or 3.310% 0-70 c crystal (x1, x2) = 14.31818 mhz l e s m a r d s , k l c u p c ) z h m ( k l c i c p ) z h m ( 00 60 3 16 . 6 63 . 3 3 pin configuration 48-pin ssop & tssop ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9148-12 pin descriptions power groups vdd = supply for pll core vdd1 = ref (0:1), x1, x2 vdd2 = pciclk_f, pciclk (0:5) vdd3 = sdram (0:5), sdram6/cpu_stop#, sdram7/pci_stop# vdd4 = 48/24mhza, 48/24mhzb vddl1 = ioapic vddl2 = cpuclk (0:3) r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1 , 2) 1 : 0 ( f e rt u ot u p t u o k c o l c e c n e r e f e r , 4 2 , 7 1 , 0 1 , 3 3 4 , 7 3 , 1 3 d n gr w p) n o m m o c ( d n u o r g 41 xn ip a c d a o l l a t s y r c l a n r e t n i s a h , t u p n i e c n e r e f e r r o l a t s y r c 52 xt u o k c a b d e e f d n a p a c d a o l l a n r e t n i s a h , t u p t u o l a t s y r c 1 x o t r o t s i s e r 6e d o mn in o i t c e l e s n o i t c n u f t u p n i 5 1 , 72 d d vr w pv 3 . 3 l a n i m o n , ) 5 : 0 ( k l c i c p , f _ k l c i c p r o f y l p p u s 8f _ k l c i c pt u o# p o t s _ i c p y b d e t c e f f a t o n , k c o l c i c p g n i n n u r e e r f 6 1 , 4 1 , 3 1 , 2 1 , 1 1 , 9) 5 : 0 ( k l c i c pt u os k c o l c i c p 8 1# 0 6 / 6 6 l e sn iu p c d n a m a r d s r o f z h m 6 . 6 6 r o z h m 0 6 s t c e l e s 9 1a t a d sn ii 2 t u p n i a t a d c 0 2k l c sn ii 2 t u p n i k c o l c c 1 24 d d vr w pv 3 . 3 l a n i m o n , b z h m 4 2 / 8 4 , a z h m 4 2 / 8 4 r o f y l p p u s 2 2a z h m 4 2 / 8 4t u oo / i r e p u s r o b s u r o f t u p t u o r e v i r d z h m 4 2 / 8 4 3 2b z h m 4 2 / 8 4t u oo / i r e p u s r o b s u r o f t u p t u o r e v i r d z h m 4 2 / 8 4 5 2d d vr w pv 3 . 3 l a n i m o n , e r o c l l p r o f y l p p u s 6 2 7 m a r d st u o) d e t c e l e s ( z h m 6 . 6 6 / 0 6 k c o l c m a r d s # p o t s _ i c pn iw o l n e h w l e v e l " 0 " c i g o l t a ) 5 : 0 ( s u b i c p s t l a h 7 2 6 m a r d st u o) d e t c e l e s ( z h m 6 . 6 6 / 0 6 k c o l c m a r d s # p o t s _ u p cn iw o l n e h w l e v e l " 0 " c i g o l t a s k c o l c u p c s t l a h 4 3 , 8 23 d d vr w p , # p o t s _ u p c / 6 m a r d s , ) 5 : 0 ( m a r d s r o f y l p p u s v 3 . 3 l a n i m o n , # p o t s _ i c p / 7 m a r d s 0 42 l d d vr w pl a n i m o n v 3 . 3 r o 5 . 2 r e h t i e , ) 3 : 0 ( k l c u p c r o f y l p p u s 8 3 , 9 3 , 1 4 , 2 4) 3 : 0 ( k l c u p ct u o2 l d d v y b d e r e w o p , t u p t u o k c o l c k l c u p c 9 2 , 0 3 , 2 3 , 3 3 , 5 3 , 6 3) 5 : 0 ( m a r d st u o) d e t c e l e s ( z h m 6 . 6 6 r o 0 6 t a k c o l c s m a r d s 4 4# n w d _ r w pn iw o l e v i t c a , p i h c n w o d s r e w o p 5 4c i p a o it u o1 l d d v y b d e r e w o p ) z h m 8 1 3 . 4 1 ( , t u p t u o k c o l c c i p a o i 6 41 l d d vr w pl a n i m o n v 3 . 3 r o 5 . 2 r e h t i e , c i p a o i r o f y l p p u s 7 4# 5 . 2 - 3 . 3 u p cn i , d d v o t p u l l u p s a h , n o i t c e l e s h t g n e r t s r e f f u b d d v 5 . 2 r o 3 . 3 . r o t s i s e r k 0 3 l a n i m o n 8 41 d d vr w pv 3 . 3 l a n i m o n , 2 x , 1 x , ) 1 : 0 ( f e r r o f y l p p u s
3 ics9148-12 power-on conditions example: a) if mode = 1, pins 26 and 27 are configured as sdram7 and sdram6 respectively. b) if mode = 0, pins 26 and 27 are configured as pci_stop# and cpu_stop# respectively. power-on default conditions at power-up and before device programming, all clocks will default to an enabled and ?on? condition. the frequencies that are t hen produced are on the mode pin as shown in the table below. k c o l c p u - r e w o p t a n o i t i d n o c t l u a f e d ) 1 : 0 ( f e r z h m 8 1 8 1 3 . 4 1 0 c i p a o i z h m 8 1 8 1 3 . 4 1 z h m 4 2 / 8 4z h m 8 4 # 0 6 / 6 6 l e se d o m# n i pn o i t p i r c s e dn o i t c n u f 11 2 4 , 1 4 , 9 3 , 8 3s k l c u p ce l b a s i d / e l b a n e g i f n o c l a i r e s / w - z h m 6 . 6 6 , 2 3 , 3 3 , 5 3 , 6 3 6 2 , 7 2 , 9 2 , 0 3 m a r d ss t u p t u o m a r d s l l a - z h m 6 . 6 6 , 2 1 , 3 1 , 4 1 , 6 1 8 , 9 , 1 1 s k l c i c pe l b a s i d / e l b a n e g i f n o c l a i r e s / w - z h m 3 . 3 3 01 2 4 , 1 4 , 9 3 , 8 3s k l c u p ce l b a s i d / e l b a n e g i f n o c l a i r e s / w - z h m 0 6 , 2 3 , 3 3 , 5 3 , 6 3 6 2 , 7 2 , 9 2 , 0 3 m a r d se l b a s i d / e l b a n e g i f n o c l a i r e s / w - z h m 0 6 , 2 1 , 3 1 , 4 1 , 6 1 8 , 9 , 1 1 s k l c i c pe l b a s i d / e l b a n e g i f n o c l a i r e s / w - z h m 0 3 10 6 2# p o t s _ i c p s k c o l c ) 5 : 0 ( i c p , t n e m e g a n a m r e w o p w o l n e h w d e p p o t s 7 2# p o t s _ u p c s k c o l c ) 5 : 0 ( u p c , t n e m e g a n a m r e w o p w o l n e h w d e p p o t s 8f _ k l c i c p r o f g n i n n u r e e r f k c o l c i c p - z h m 3 . 3 3 - z h m 3 . 3 3 t n e m e g a n a m r e w o p 2 4 , 1 4 , 9 3 , 8 3s k l c u p c d n a l o r t n o c p o t s l a n r e t x e / w s k c o l c u p c - z h m 6 . 6 6 . e l b a s i d / e l b a n e l a u d i v i d n i g i f n o c l a i r e s , 2 3 , 3 3 , 5 3 , 6 3 9 2 , 0 3 m a r d s l a u d i v i d n i g i f n o c l a i r e s / w s k c o l c m a r d s - z h m 6 . 6 6 . e l b a s i d / e l b a n e , 2 1 , 3 1 , 4 1 , 6 1 9 , 1 1 s k l c i c p d n a l o r t n o c p o t s l a n r e t x e / w s k c o l c i c p - z h m 3 . 3 3 . e l b a s i d / e l b a n e l a u d i v i d n i g i f n o c l a i r e s 00 6 2# p o t s _ i c p s k c o l c ) 5 : 0 ( i c p , t n e m e g a n a m r e w o p w o l n e h w d e p p o t s 7 2# p o t s _ u p c s k c o l c ) 5 : 0 ( u p c , t n e m e g a n a m r e w o p w o l n e h w d e p p o t s 8f _ k l c i c p r e w o p r o f g n i n n u r e e r f k c o l c i c p - z h m 0 3 t n e m e g a n a m 2 4 , 1 4 , 9 3 , 8 3s k l c u p c d n a l o r t n o c p o t s l a n r e t x e / w s k c o l c u p c - z h m 0 6 . e l b a s i d / e l b a n e l a u d i v i d n i g i f n o c l a i r e s , 2 3 , 3 3 , 5 3 , 6 3 9 2 , 0 3 m a r d s l a u d i v i d n i g i f n o c l a i r e s / w s k c o l c m a r d s - z h m 0 6 . e l b a s i d / e l b a n e , 2 1 , 3 1 , 4 1 , 6 1 9 , 1 1 s k l c i c p d n a l o r t n o c p o t s l a n r e t x e / w s k c o l c i c p - z h m 0 3 . e l b a s i d / e l b a n e l a u d i v i d n i g i f n o c l a i r e s
4 ics9148-12 technical pin function descriptions vdd(1,2,3,4) this is the power supply to the internal core logic of the device as well as the clock output buffers for ref(0:1), pciclk, 48/24mhza/b and sdram(0:7). this pin operates at 3.3v volts. clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels for the clocks, please consult the dc parameter table in this data sheet. vddl1,2 this is the power supplies for the cpuclk and ioapci output buffers. the voltage level for these outputs may be 2.5 or 3.3volts. clocks from the buffers that each supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels of these clocks, please consult the dc parameter table in this data sheet. gnd this is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. x1 this input pin serves one of two functions. when the device is used with a crystal, x1 acts as the input pin for the reference signal that comes from the discrete crystal. when the device is driven by an external clock signal, x1 is the device input pin for that reference clock. this pin also implements an internal crystal loading capacitor that is connected to ground. see the data tables for the value of this capacitor. x2 this output pin is used only when the device uses a crystal as the reference frequency source. in this mode of operation, x2 is an output signal that drives (or excites) the discrete crystal. the x2 pin will also implement an internal crystal loading capacitor that is connected to ground. see the data sheet for the value of this capacitor. cpuclk (0:3) these output pins are the clock outputs that drive processor and other cpu related circuitry that requires clocks which are in tight skew tolerance with the cpu clock. the voltage swing of these clocks are controlled by the voltage level applied to the vddl2 pin of the device. see the functionality table for a list of the specific frequencies that are available for these clocks and the selection codes to produce them. sdram(0:7) these output clocks are use to drive dynamic ram?s and are low skew copies of the cpu clocks. the voltage swing of the sdram?s output is controlled by the supply voltage that is applied to vdd3 of the device, operates at 3.3 volts. 48/24mhza, b this is a fixed frequency clock output that is typically used to drive super i/o devices. outputs a and b are defined as 24 or 48mhz by i 2 c register (see table). ioapic this output is a fixed frequency output clock that runs at the reference input (typically 14.31818mhz) . its voltage level swing is controlled by vddl1 and may operate at 2.5 or 3.3volts. ref(0:1) the ref outputs are fixed frequency clocks that run at the same frequency as the input reference clock x1 or the crystal (typically 14.31818mhz) attached across x1 and x2. pciclk_f this output is equal to pciclk(0:5) and is free running, and will not be stopped by pci_stp#. pciclk (0:5) these output clocks generate all the pci timing requirements for a pentium/pro based system. they conform to the current pci specification. they run at 1/2 cpu frequency. select 66.6/60mhz# this input pin controls the frequency of the clocks at the cpu, pciclk and sdram output pins. if a logic ?1? value is present on this pin, the 66.6 mhz clock will be selected. if a logic ?0? is used, the 60mhz frequency will be selected. mode this input pin is used to select the input function of the i/ o pins. an active low will place the i/o pins in the input mode and enable those stop clock functions.
5 ics9148-12 cpu3.3_2.5# this input pin controls the cpu and ioapic output buffer strength for skew matching cpu and sdram outputs to compensate for the external vddl supply condition. it is important to use this function when selecting power supply requirements for vddl1,2. a logic ?0? (ground) will indicate 2.5v operation and a logic ?1? will indicate 3.3v operation. this pin has an internal pullup resistor to vdd. pwr_dwn# this is an asynchronous active low input pin used to power down the device into a low power state by not removing the power supply. the internal clocks are disabled and the vco and crystal are stopped. powered down will also place all the outputs in a low state at the end of their current cycle. the latency of power down will not be greater than 3ms. the i 2 c inputs will be tri-stated and the device will retain all programming information. this input pin only valid when mode=0 (power management mode) cpu_stop# this is a synchronous active low input pin used to stop the cpuclk clocks in an active low state. all other clocks including sdram clocks will continue to run while this function is enabled. the cpuclk?s will have a turn on latency of at least 3 cpu clocks. this input pin only valid when mode=0 (power management mode) pci_stop# this is a synchronous active low input pin used to stop the pciclk clocks in an active low state. it will not effect pciclk_f nor any other outputs. this input pin only valid when mode=0 (power management mode) i 2 c the sdata and sclock inputs are use to program the device. the clock generator is a slave-receiver device in the i 2 c protocol. it will allow read-back of the registers. see configuration map for register functions. the i 2 c specification in philips i 2 c peripherals data handbook (1996) should be followed. technical pin function descriptions
6 ics9148-12 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 5 ? ics clock will acknowledge each byte one at a time . ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controler (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 5 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ack byte 2 ac k byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write:
7 ics9148-12 notes: 1. tclk is a test clock driven on the x1 (crystal in pin) input during test mode. y t i l a n o i t c n u fu p c , i c p f _ i c p m a r d sf e rc i p a o i z h m 4 2 n o i t c e l e s z h m 8 4 n o i t c e l e s e t a t s i r tz - i hz - i hz - i hz - i hz - i hz - i hz - i h e d o m t s e t2 / k l c t 1 4 / k l c t 1 2 / k l c t 1 k l c t 1 k l c t 1 4 / k l c t 1 2 / k l c t 1 select functions serial configuration command bitmaps byte 0: functional and frequency select clock register (default on bits 7, 6, 5, 4, 1, 0 = 0) (default on bits 3, 2 = 1) note: pwd = power-up default t i b# n i pn o i t p i r c s e dd w p 7 t i b- d e v r e s e r0 6 t i b- n o i t a r e p o l a m r o n r o f 0 e b t s u m0 5 t i b- e p y t s l o r t n o c , m u r t c e p s d a e r p s n i ) d a e r p s n w o d = 1 , d e r e t n e c = 0 ( 0 4 t i b g n i d a e r p s s l o r t n o c , m u r t c e p s d a e r p s n i ) % 6 . 0 = 1 % 8 . 1 = 0 ( 0 3 t i b3 2z h m 4 2 = 0 , z h m 8 4 = 1 ) t c e l e s y c n e u q e r f ( z h m 4 2 / 8 41 2 t i b2 2z h m 4 2 = 0 , z h m 8 4 = 1 ) t c e l e s y c n e u q e r f ( z h m 4 2 / 8 41 1 t i b 0 t i b - 1 t i b 1 1 0 0 0 t i b e t a t s - i r t - 1 e l b a n e m u r t c e p s d a e r p s - 0 e d o m t s e t - 1 n o i t a r e p o l a m r o n - 0 0 0
8 ics9148-12 byte 1: cpu, 24/48 mhz clock register notes: 1 = enabled; 0 = disabled, outputs held low byte 2: pciclk clock register byte 4: sdram clock register notes: 1 = enabled; 0 = disabled, outputs held low notes: 1 = enabled; 0 = disabled, outputs held low t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b81 ) t c a n i / t c a ( f _ k l c i c p 5 t i b6 11 ) t c a n i / t c a ( 5 k l c i c p 4 t i b4 11 ) t c a n i / t c a ( 4 k l c i c p 3 t i b3 11 ) t c a n i / t c a ( 3 k l c i c p 2 t i b2 11 ) t c a n i / t c a ( 2 k l c i c p 1 t i b1 11 ) t c a n i / t c a ( 1 k l c i c p 0 t i b91 ) t c a n i / t c a ( 0 k l c i c p t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-1 d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b3 21 ) t c a n i / t c a ( z h m 4 2 / 8 4 6 t i b2 21 ) t c a n i / t c a ( z h m 4 2 / 8 4 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b8 31 ) t c a n i / t c a ( 3 k l c u p c 2 t i b9 31 ) t c a n i / t c a ( 2 k l c u p c 1 t i b1 41 ) t c a n i / t c a ( 1 k l c u p c 0 t i b2 41 ) t c a n i / t c a ( 0 k l c u p c byte 3: sdram clock register notes: 1 = enabled; 0 = disabled, outputs held low t i b# n i pd w pn o i t p i r c s e d 7 t i b6 21 ) t c a n i / t c a ( 7 m a r d s 6 t i b7 21 ) t c a n i / t c a ( 6 m a r d s 5 t i b9 21 ) t c a n i / t c a ( 5 m a r d s 4 t i b0 31 ) t c a n i / t c a ( 4 m a r d s 3 t i b2 31 ) t c a n i / t c a ( 3 m a r d s 2 t i b3 31 ) t c a n i / t c a ( 2 m a r d s 1 t i b5 31 ) t c a n i / t c a ( 1 m a r d s 0 t i b6 31 ) t c a n i / t c a ( 0 m a r d s note: pwd = power-up default byte 5: peripheral clock register notes: 1 = enabled; 0 = disabled, outputs held low t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b5 41 ) t c a n i / t c a ( 0 c i p a o i 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b11 ) t c a n i / t c a ( 1 f e r 0 t i b21 ) t c a n i / t c a ( 0 f e r note: pwd = power-up default byte 6: optional register for future notes: 1. byte 6 is reserved by integrated circuit systems for future applications. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-1 d e v r e s e r
9 ics9148-12 power management ics9148-12 power management requirements clock enable configuration full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. during power up and power down operations using the pwr pd# select pin will not cause clocks of a short or longer pulse than that of the running clock. the first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. board routing and signal loading may have a large impact on the initial clock distortion also. notes. 1. clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device . 3. power up latency is when pd# goes inactive (high) to when the first valid clocks are output by the device. 4. power down has controlled clock counts applicable to cpuclk, sdram, pciclk only. the ref and ioapic will be stopped independant of these. l a n g i se t a t s l a n g i s y c n e t a l g n i n n u r e e r f f o s e g d e g n i s i r f o . o n k l c i c p # p o t s _ u p c) d e l b a s i d ( 0 2 1 ) d e l b a n e ( 1 1 1 # p o t s _ i c p) d e l b a s i d ( 0 2 1 ) d e l b a n e ( 1 1 1 # n w d _ r w p) n o i t a r e p o l a m r o n ( 1 3 s m 3 ) n w o d r e w o p ( 0 4 x a m 2 # p o t s _ u p c# p o t s _ i c p# n w d _ r w pk l c u p ck l c i c p , s k c o l c r e h t o , m a r d s , f e r , s c i p a o i a z h m 4 2 / 8 4 b z h m 4 2 / 8 4 l a t s y r cs o c v xx 0 w o lw o ld e p p o t sf f of f o 00 1 w o lw o lg n i n n u rg n i n n u rg n i n n u r 011 w o lz h m 0 3 / 3 . 3 3g n i n n u rg n i n n u rg n i n n u r 10 1 z h m 0 6 / 6 . 6 6w o lg n i n n u rg n i n n u rg n i n n u r 11 1 z h m 0 6 / 6 . 6 6z h m 0 3 / 3 . 3 3g n i n n u rg n i n n u rg n i n n u r
10 ics9148-12 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9148-12 . it is used to turn off the pciclk (0:5) clocks for low power operation. pci_stop# is synchronized by the ics9148-12 internally. the minimum that the pciclk (0:5) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:5) clocks. pciclk (0:5) clocks are stopped in a low state and started with a full high pul se width guaranteed. pciclk (0:5) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. cpu_stop# timing diagram cpustop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics9148-12 . the minimum that the cpuclk is enabled (cpu_stop# high pulse) is 100 cpuclks. all other clocks will continue to run while the cpuclks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. (drawing shown on next page.) notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics9148-12 . 3. all other clocks continue to run undisturbed. 4. pd# and pci_stop# are shown in a high (true) state.
11 ics9148-12 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal is synchronized internal by the ics9148-12 prior to its control action of powering down the clock synthesizer. internal clocks will not be running after the device is put in power down state. when pd# is active (low) all clocks are driven to a low state and held prior to turning off the vcos and the crystal oscillator. the pow er on latency is guaranteed to be less than 3ms. the power down latency is less than three cpuclk cycles. pci_stop# and cpu_stop# are don?t care signals during the power down operations. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9148 device). 2. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside the ics9148. 3. the shaded sections on the vco and the crystal signals indicate an active clock is being generated. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9148 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9148. 3. all other clocks continue to run undisturbed. 4. pd# and cpu_stop# are shown in a high (true) state.
12 ics9148-12 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol c onditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 m a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 m a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 m a operating i dd3.3op c l = 0 pf; select @ 66m 60 100 ma supply current power down i dd3.3pd c l = 0 pf; with input address to vdd or gnd 400 600 m a supply current input frequency f i v dd = 3.3 v; 14.318 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew 1 t cpu-sdram1 v t = 1.5 v 200 500 ps t cpu-pci1 v t = 1.5 v; 1.5 3.2 4.5 ns 1 guarenteed by design, not 100% tested in production. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5op c l = 0 pf; select @ 66m 5 20 ma supply current power down i dd2.5pd c l = 0 pf; 0.21 1.0 m a supply current skew 1 t cpu-sdram2 v t = 1.5 v; v tl = 1.25 v; sdram leads 150 500 ps t cp u-p ci2 v t = 1.5 v; v tl = 1.25 v; cpu leads 12.84 ns 1 guarenteed by design, not 100% tested in production. absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
13 ics9148-12 electrical characteristics - cpu t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwis e s tated) parameter symbol conditions min typ max units output frequency f o2 60 66 mhz output impedance r dsp2a 1 v o = v dd *(0.5) 10 20 w output impedance r dsn2a 1 v o = v dd *(0.5) 10 20 w output high voltage v oh2a i oh = -28 ma 2.4 2.5 v output low voltage v ol2a i ol = 27 ma 0.35 0.4 v output high current i oh2a v oh = 2.0 v -52 -48 ma output low current i ol2a v ol = 0.8 v 49.3 59 ma ris e time t r2a 1 v ol = 0.4 v, v oh = 2.4 v 1.1 2.85 ns fall time t f2 a 1 v oh = 2.4 v, v ol = 0.4 v 0.95 2.85 ns duty cycle d t2a 1 v t = 1.5 v 45 51 55 % skew t sk2a 1 v t = 1.5 v 80 250 ps t jcyc-cyc2a 1 v t = 1.5 v 170 250 ps jitter t j1s2a 1 v t = 1.5 v 60 150 ps t jabs2a 1 v t = 1.5 v -250 100 +250 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o2 60 66 mhz output impedance r dsp2b 1 v o = v dd *(0.5) 10 20 w output impedance r dsn2b 1 v o = v dd *(0.5) 10 20 w output high voltage v oh2b i oh = -8.0 ma 2.1 2.15 v output low voltage v ol2b i ol = 21 ma 0.3 0.4 v output high current i oh2b v oh = 1.8 v -22 -18 ma output low current i ol2b v ol = 0.5 v 33 36 ma ris e time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 1.2 1.5 ns fall time t f2 b 1 v oh = 2.0 v, v ol = 0.4 v 0.95 1.3 ns duty cycle d t2b 1 v t = 1.25 v 45 50 55 ns skew t sk2b 1 v t = 1.25 v 60 250 ps t jcyc-cyc2b 1 v t = 1.25 v 150 250 ps jitter t j1s2b 1 v t = 1.25 v 50 150 ps t jabs2b 1 v t = 1.25 v -250 80 +250 ps 1 guarenteed by design, not 100% tested in production.
14 ics9148-12 electrical characteristics - pci t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o1 30 - 33 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 55 w output impedance r dsn1 1 v o = v dd *(0.5) 12 55 w output high voltage v oh1 i oh = -14.5 ma 2.4 2.7 v output low voltage v ol1 i ol = 9.4 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -47 -22 ma output low current i ol1 v ol = 0.8 v 17.1 47.5 ma ris e time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1.5 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1.1 2 ns duty cycle d t1 1 v t = 1.5 v 45 51 55 % skew t sk1 1 v t = 1.5 v 100 250 ps jitter t j1s1 1 v t = 1.5 v 50 150 ps t jabs1 1 v t = 1.5 v -250 120 250 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 30 pf (unless otherwis e s tated) parameter symbol conditions min typ max units output frequency f o3 60 66 mhz output impedance r dsp3 1 v o = v dd *(0.5) 10 24 w output impedance r dsn3 1 v o = v dd *(0.5) 10 24 w output high voltage v oh3 i oh = -24 ma 2.4 2.5 v output low voltage v ol3 i ol = 23 ma 0.35 0.4 v output high current i oh3 v oh = 2.0 v -47 -40 ma output low current i ol3 v ol = 0.8 v 41 47.5 ma ris e time t r3 1 v ol = 0.4 v, v oh = 2.4 v 1.45 1.7 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 1.2 1.5 ns duty cycle d t3 1 v t = 1.5 v 45 51 55 % skew t sk3 1 v t = 1.5 v 80 250 ps jitter t j1s3 1 v t = 1.5 v 40 150 ps t jabs3 1 v t = 1.5 v -250 - 250 ps 1 guarenteed by design, not 100% tested in production.
15 ics9148-12 electrical characteristics - ioapic t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwis e s tated) parameter symbol conditions min typ max units output frequency f o4 14.318 mhz output impedance r dsp4a 1 v o = v dd *(0.5) 10 30 w output impedance r dsn4a 1 v o = v dd *(0.5) 10 30 w output high voltage v oh4a i oh = -13 ma 2.5 2.6 v output low voltage v ol4a i ol = 18 ma 0.35 0.4 v output high current i oh4a v oh = 2.0 v -29 -23 ma output low current i ol4a v ol = 0.8 v 33 37 ma ris e time t r4a 1 v ol = 0.4 v, v oh = 2.4 v 1.1 2 ns fall time t f4 a 1 v oh = 2.4 v, v ol = 0.4 v 1.6 2 ns duty cycle d t4a 1 v t = 1.5 v 45 51 55 % jitter t j1s4a 1 v t = 1.5 v 160 350 ps t jabs4a 1 v t = 1.5 v -600 - 600 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - ioapic t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o4 60 66 mhz output impedance r dsp4b 1 v o = v dd *(0.5) 10 30 w output impedance r dsn4b 1 v o = v dd *(0.5) 10 30 w output high voltage v oh4\b i oh = -5.5 ma 2.1 2.2 v output low voltage v ol4b i ol = 9.0 ma 0.25 0.3 v output high current i oh4b v oh = 1.7 v -17 -15 ma output low current i ol4b v ol = 0.7 v 15 16 ma ris e time t r4b 1 v ol = 0.4 v, v oh = 2.0 v 1.4 1.6 ns fall time t f4 b 1 v oh = 2.0 v, v ol = 0.4 v 1.1 1.6 ns duty cycle d t4b 1 v t = 1.25 v 40 53 60 % jitter t j1s4b 1 v t = 1.25 v 130 300 ps t jabs4b 1 v t = 1.25 v -700 - 700 ps 1 guarenteed by design, not 100% tested in production.
16 ics9148-12 electrical characteristics - ref0 t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 45 pf (unless otherwis e s tated) parameter symbol conditions min typ max units output frequency f o7 14.318 mhz output impedance r dsp7 v o = v dd *(0.5) 10 24 w output impedance r dsn7 v o = v dd *(0.5) 10 24 w output high voltage v oh7 i oh = -24 ma 2.4 2.5 v output low voltage v ol7 i ol = 23 ma 0.35 0.4 v output high current i oh7 v oh = 2.0 v -47 -40 ma output low current i ol7 v ol = 0.8 v 41 47.5 ma ris e time t r7 1 v ol = 0.4 v, v oh = 2.4 v 1.8 2 ns fall time t f7 1 v oh = 2.4 v, v ol = 0.4 v 1.4 2 ns duty cycle d t7 1 v t = 1.5 v 45 52 45 % jitter t j1s7 1 v t = 1.5 v 150 350 ps t jabs7 1 v t = 1.5 v -600 - 600 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - 24m, 48m, ref(1:2) t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 -20 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o24m 24 mhz output frequency f o48m 48 mhz output frequency f oref 14.318 mhz output impedance r dsp5 1 v o = v dd *(0.5) 20 60 w output impedance r dsn5 1 v o = v dd *(0.5) 20 60 w output high voltage v oh5 i oh = -16 ma 2.4 2.5 v output low voltage v ol5 i ol = 9 ma 0.2 0.4 v output high current i oh5 v oh = 2.0 v -29 -22 ma output low current i ol5 v ol = 0.8 v 16 25 ma ris e time t r5 1 v ol = 0.4 v, v oh = 2.4 v 1.8 4 ns fall time t f5 1 v oh = 2.4 v, v ol = 0.4 v 1.7 4 ns duty cycle d t5 1 v t = 1.5 v 45 51 55 % jitter t j1s5a 1 v t = 1.5 v; fixed clocks 50 150 ps t j1s5b 1 v t = 1.5 v; ref clocks 150 350 t jabs5a 1 v t = 1.5 v; fixed clocks -250 120 250 t jabs5b 1 v t = 1.5 v; ref clocks -600 - 600 ps 1 guarenteed by design, not 100% tested in production.
17 ics9148-12 this table in inches ssop package l o b m y s s n o i s n e m i d n o m m o c s n o i t a i r a v d n . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .1 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 . 2 a8 8 0 .0 9 0 .2 9 0 . b8 0 0 .0 1 0 .5 3 1 0 . c5 0 0 .6 0 0 .5 8 0 0 . ds n o i t a i r a v e e s e2 9 2 .6 9 2 .9 9 2 . ec s b 5 2 0 . 0 h0 0 4 .6 0 4 .0 1 4 . h0 1 0 .3 1 0 .6 1 0 . l4 2 0 .2 3 0 .0 4 0 . ns n o i t a i r a v e e s 0 5 8 x5 8 0 .3 9 0 .0 0 1 . ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information ics9148 y f-12 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp
18 ics9148-12 240 mil (6.10mm)tssop package ordering information ics9148g-12 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. diminisions are in millimeters 240tssop_an l o b m y s n o m m o c s n o i s n e m i d s n o i t a i r a v n d . n i m. m o n. x a m. n i m. m o nx a m a0 1 . 10 4 . 2 10 5 . 2 10 6 . 2 18 4 1 a5 0 . 05 1 . 00 9 . 3 10 0 . 4 10 1 . 4 16 5 2 a5 8 . 00 9 . 05 9 . 0 b7 1 . 07 2 . 0 c9 0 . 00 2 . 0 ds n o i t a i r a v e e s 1 e0 0 . 60 1 . 60 2 . 6 ec s b 0 5 . 0 ec s b 0 1 . 8 l0 5 . 00 6 . 00 7 . 0 ns n o i t a i r a v e e s a 0 8 pattern number (2 or 3 digit number for parts with rom code patterns) package type g=tssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx g - ppp

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